As it is well known, the more widespread use of multimedia applications and the expansion of these applications need a greater amount of data to be manipulated and to be stored within the shortest time possible.
To fulfill this need, non volatile memory structures use matrixes of memory cells, for example of the NOR Flash type.
A main advantage of NOR Flash memories is that an update operation of a group of columns is carried out in parallel and simultaneously on all the selected cells belonging to each row of the group.
FIG. 1 shows, by means of a flow chart, a method for programming a group of columns of an architecture with Flash-Nor memory cells.
A programming cycle comprising an alternated repetition of programming and verify steps allows to program suitable selected cells.
During the programming step, the selected cells are biased at suitable programming voltages and subjected to a pulses sequence until a desired threshold is attained.
A non volatile memory device architecture currently used is shown in FIG. 2. The architecture 1 comprises a partition 2 of a matrix of memory cells associated with a control circuit structure 4 for the management of the programming of the entire partition 2.
The partition 2 is divided into a plurality of sectors 10 adjacent to each other and each comprising a predetermined number of columns or bit-lines and a same number of rows or word-lines. Each sector 10 is associated with a respective logic circuit 6.
In particular, each sector 10 and a corresponding logic circuit 6, as shown in FIG. 3, define a block 5 to be programmed.
Each logic circuit 6 comprises a high voltage circuit HV connected to a P_pulse signal for the control of a program load PL for pulse programming of selected cells of the sector 10.
“Programming per row” is programming which sequentially selects and programs cells belonging to a same row or word line WL.
For each block 5 to be programmed, the cells being programmed belong to a same row or word-line WL, selected in the usual way, and to columns sequentially selected by means of suitable select signals YN,Y0 generated by a decoder 12.
In the embodiment shown, a cell matrix is considered with three number of metallizations and, in particular, a first lower level M1 and a level M3 where a plurality of columns or local bit-lines LBL and a plurality of global bit-lines GBL are respectively defined, and a second level M2 where the rows or word-lines WL are defined.
In the example of FIG. 3, eight global bit-lines GBL GBLi i=0, . . . 7 and 32 local bit-lines LBLi are connected in groups of four to one global bit-line GBLi.
The global bit-lines GBLi i=0, . . . 7 are enabled by means of a first select signal YNi, generated by the decoder 12, which activates a corresponding first enable transistor Ti i=0, . . . 7 interposed between each global bit-line GBLi i=0, . . . 7 and a control line 50 shared by all the global bit-lines GBLi.
For each global bit-line GBLi i=0, . . . 7, corresponding local bit-lines LBLij j=0 . . . 3, is enabled by a same second select signal YO, generated by the decoder 12, which activates a corresponding second enable transistor Tij i=0, . . . 7 j=0, . . . 3 interposed between each local bit-line LBLij and the corresponding global bit-line GBLi.
The block 5 to be programmed of FIG. 3 also has a discharge circuit 13 comprising a discharge transistor Ts, interposed between the control line 50 and a ground reference, controlled by a discharge signal YNS. The discharge transistor Ts is activated at the end of the programming of a cell by means of programming pulses generated by the program load PL and allows to discharge possible high voltages present on the local bit-line LBLij which comprises this programmed cell.
The block 5 to be programmed also comprises sense amplifiers SA to read the programmed cells of the sector 10.
The architecture of such blocks 5 to be programmed allows a programming parallelism which depends on the number of the present program loads PL. If these program loads PL are equal to the number of sense amplifiers SA, the same number of cells can be simultaneously programmed and read in parallel.
For each block 5 to be programmed a programming cycle between two successive verify steps provides the pulses programming of all the cells belonging to a same enabled word-line.
In particular, the first select signal YNi sequentially enables all the global bit-lines GBLi of the sector 10 while the second select signal YOj enables a same local bit-line LBLij for each group.
The signal YOj switches when all the local bit-lines LBLij of a group have been enabled, i.e., after a complete sequential switch of the first select signal YNi.
Considering an entire partition 2 of the matrix, the circuit structure 4 allows, if requested, a programming parallelism between more devices 5 and the maximum parallelism is defined by the number of the program loads PL.
Moreover, in this case, the first select signal YNi is unique for the entire partition 2 while the second select signal YOj is relative to each sector 10 of the partition 2.
FIG. 4 shows the waveforms of the signals used during the programming step, in a sector 10, relative to the storage of two cells belonging to a same word-line and belonging to corresponding local bit-lines LBLij of the group respectively associated with global bit-lines alternatively activated by the first signal YN3 and by the first select signal YN4.
Let us suppose, for example, that j is equal to 0 and thus the active local bit-lines are LBL30 and LBL40.
The programming provides a first select step H1 where the first select signal YN3 is activated, i.e., in the specific case brought to the high logic level, this signal enables the global bit-line GBL3 by activating the second select transistor T3.
Subsequently, a second real programming step H2 is provided during which the program load PL is updated by the logic circuit 6 and prepared for the programming of the enabled local bit-line LBL30 sending a programming pulse if the voltage value in the cell is not the desired one.
Thus, a third discharge step H3 is provided during which the discharge signal YNS, activated, controls the discharge transistor Ts discharging the possible high voltage present in the local bit-line LBL30.
Then, a new first step H1 follows and the deactivation of the discharge signal YNS the deactivation of the first select signal YN3 and the simultaneous activation of the signal YN4 which controls the second transistor T4 enabling the global bit-line GBL4 to allow the programming of the cell belonging to the local bit-line LBL40 already enabled by the second select signal YO0.
A new second step H2 allows to control the program load PL and thus to apply pulses, if necessary, to the active cell.
Subsequently, a new third step H3 allows to discharge the possible high voltages accumulated in the local bit-line LBL40.
The programming goes on through successive steps so as to program all the cells of the sector 10 belonging to a same row WL.
The memory device previously described, although satisfactory, shows however some drawbacks.
In fact, the time of the third discharge step H3 is particularly high and this affects the programming speed in an unfavorable way. Considering for example a discharge time of the bit-line of the order of some tens of nanoseconds, the contribution is relevant already with a programming pulse of the program load PL of 300 ns.